David Emelu

Real-time embedded system fusing thermal infrared and visible-light imagery into a heads-up display overlay for enhanced situational awareness

Hardware: NVIDIA Jetson Nano, FLIR Lepton 3.5, Raspberry Pi HQ Cam · Software: Embedded C, YOLOv5 · Documentation: LaTeX

Standard visual imaging systems lose detail in low-light or obscured environments, posing a disproportionate safety risk to motorists. The project required designing a system that fuses thermal and visible imagery in real time to support environments where conventional cameras are insufficient.

Defined system requirements and designed a multimodal sensor interface. Combined thermal capabilities of the FLIR sensor with the high-resolution context of the Pi HQ camera. Processed inputs in real-time using an NVIDIA Jetson Nano running a YOLOv5 neural network for pedestrian and wildlife detection.

Animal-themed embedded clock radio featuring FM tuning, timekeeping, custom PCB fabrication, and a 3D-printed mechanical enclosure

EDA: KiCad · CAD: SolidWorks · MCU: Raspberry Pi Pico · Peripherals: DS3231 RTC, RDA5807M FM Tuner, I2C OLED · Test: Oscilloscope

Required a complete embedded hardware design exercise covering the full engineering workflow to integrate core timekeeping and FM radio functionalities into a cohesive, user-friendly device.

Developed firmware in C/C++ to interface the Pi Pico with the RTC and FM modules via I2C, implementing pushbutton control for alarms and tuning. Completed the full hardware lifecycle: captured schematics, performed 2-layer PCB layout with routing in KiCad, sent boards for fabrication, and assembled the system within a custom SolidWorks-modeled 3D-printed housing.

Real-time embedded system on STM32F4 featuring a deterministic traffic controller and a custom Earliest Deadline First (EDF) scheduler

MCU: STM32F4 Discovery (ARM Cortex-M4) · OS: FreeRTOS · Tools: Oscilloscope, Logic Analyzer · Documentation: LaTeX

Implement deterministic multitasking to manage a complex traffic control system, and subsequently engineer a custom deadline-driven scheduling algorithm for hard real-time tasks.

First designed a traffic light controller utilizing ADC polling, hardware shift registers, and queue-based inter-task communication. Next, extended the FreeRTOS kernel to implement an Earliest Deadline First (EDF) scheduler, dynamically manipulating task priorities to guarantee execution of processes with the nearest absolute deadlines.

Mathematical modeling and simulation of a 6-bus power system for steady-state load flow and bolted 3-phase fault analysis

Software: MATLAB, PowerWorld Simulator · Analysis: Newton-Raphson method, Symmetrical Components, Per-Unit notation

Analyze a multi-bus power distribution network to determine steady-state voltage stability, identify constraint violations under loading scenarios, and compute fault currents to evaluate system resilience.

Developed a custom MATLAB script implementing the Newton-Raphson method to solve complex power flow matrices. Calculated system voltages and performed bolted 3-phase fault analysis. Validated the custom mathematical models by comparing output data directly against simulations run in the industry-standard PowerWorld Simulator.

Bare-metal embedded system on STM32F0: analog signal processing (ADC/DAC), hardware timer-based frequency measurement, and SPI OLED control

MCU: STM32F0 Discovery (ARM Cortex-M0) · Peripherals: SSD1306 OLED, NE555 Timer, 4N35 Optocoupler · Protocols: SPI · Concepts: Register-Level I/O, EXTI

Design and implement an embedded system on the STM32F0 Discovery Board that measures, processes, and controls external signals in real time. It must integrate analog-to-digital conversion, digital-to-analog conversion, external interrupt handling, frequency measurement, and SPI-based display control.

Programmed STM32 peripherals at the register level. Utilized continuous ADC polling to read a potentiometer, mapping the value to a DAC output to drive a 555 timer via an optocoupler. Configured hardware timers (TIM2) and external interrupts (EXTI) to measure square wave frequencies from the 555 timer and a function generator. Developed a custom SPI driver to render real-time resistance and frequency data on an SSD1306 OLED display.

Communication system laboratory: implementation and analysis of AM/FM analog modulation and ASK/FSK/PSK digital modulation schemes with noise characterisation

Software: MATLAB · Analysis: SNR calculations, BER curves, channel capacity · Output: modulation simulation results, project reports

Design, simulate, and analyse analog and digital communication systems to demonstrate understanding of modulation schemes, signal detection, and channel noise effects in practical transmission scenarios.

Implemented AM, FM, ASK, FSK, and PSK modulation schemes in MATLAB. Characterised receiver performance under AWGN channel noise using BER analysis. Applied Shannon channel capacity theory to evaluate theoretical performance limits. Two structured project reports document simulation methodology and results.

Hardware implementation of a 16-bit pipelined processor on FPGA, alongside analytical study of memory hierarchies, microarchitecture, and out-of-order execution in modern CPUs

FPGA: Digilent Basys3 (Xilinx Artix-7) · HDL: VHDL · Synthesis & Implementation: Vivado · Simulation: Vivado Simulator (waveform viewer)

Implement a 16-bit pipelined processor supporting three instruction formats (A, B, L) in VHDL, and separately analyse advanced CPU subsystems including cache memory hierarchies (AMAT/CPI), scoreboard-based out-of-order execution, branch prediction, and the Intel P6 and NetBurst (Pentium 4) microarchitectures.

Designed and verified a multi-stage pipelined datapath in VHDL targeting the Basys3 FPGA, with Format A (ALU) and Format B (branch/memory) instruction demos completed and Format L (load/store extended).

ISR-driven conveyor belt sorting system: multi-sensor classification pipeline, DC motor belt with PWM speed control, stepper-driven rotating tray with S-curve acceleration, and interrupt-based real-time control firmware

MCU: ATmega2560 @ 8 MHz (CLKPR prescaled) · Sensors: OPB819Z optical exit, OPB742 reflective/ADC, SS400 Hall Effect · Actuators: DC gearmotor (Timer 0 Fast PWM), unipolar stepper (PORTA full-step + S-curve ramp) · Software: Embedded C, AVR-GCC toolchain · Tools: oscilloscope, L298 H-bridge driver, KiCad

Design and build a real-time mechatronic sorting system capable of classifying four material types: Steel, Aluminum, White Plastic, and Black Plastic as objects travel along a conveyor belt, then routing each object to the correct tray position without misclassification under back-to-back object conditions.

Built around an ATmega2560 with a FIFO linked-list queue managing belt objects. Classification occurs in the INT4 falling-edge ISR using ADC minimum-tracking over the sensor window and Hall Effect detection; a pending_valid/pending_code decoupling pattern prevents race conditions between closely spaced objects. Tray positioning uses full-step stepper patterns on PORTA with an S-curve ramp and Hall Effect homing on INT5, gated by a homing_active flag to suppress spurious resets during sorting. Final design documentation (~22 pages, PDF) covers system architecture, sensor calibration, firmware design, and test results.

Hybrid off-grid energy system: solar PV primary + vertical-axis wind turbine seasonal support + LiFePO4 battery storage + smart telemetry, supporting 2-4 e-bike charges/day year-round

Analysis: load-first sizing methodology · Solar: PV array sizing for Victoria, BC insolation · Battery: LiFePO4 buffer storage · Telemetry: micro-weather sensors · Structure: modular steel frame with solar canopy

The BC Sustainable Energy Association and UVic Institute for Integrated Energy Systems challenged teams to design a fully off-grid renewable e-bike charging station for deployment on the UVic campus, operating without grid connection in Victoria's variable climate.

Applied a load-first sizing methodology to guarantee reliable year-round operation. Designed a hybrid energy architecture: solar PV as the primary source, vertical-axis wind turbines for seasonal support, and LiFePO4 battery storage for energy buffering. Integrated a micro-weather telemetry system enabling adaptive charging strategies and operating the station as both an energy infrastructure asset and a data collection node. Physical design featured a modular steel-frame structure with solar canopy, weatherproof power enclosures, and universal charging ports, optimised for scalability and minimal on-site installation time.

Tied for 2nd place. Solution recognised for cost-performance balance and smart telemetry innovation.

2D structural documentation, field-survey data transferred to ANSI-compliant AutoCAD drawings

Software: AutoCAD · Field: tape measure + survey notebook · Standards: ANSI Y14.5 layering and annotation

The Haisla Bridge rehabilitation project required accurate 2D documentation of existing conditions and a material cost estimate for paint work before any design or procurement could proceed.

Conducted on-site field measurements of the bridge structure; transferred survey data to 2D AutoCAD drawings using ANSI-compliant layering and annotation conventions. Performed a detailed paint quantity take-off from the drawings to produce a material cost estimate for the rehabilitation scope.

Multi-route ridership dataset, statistical performance analysis against BC Transit service standard targets

Software: Microsoft Excel · Data: BC Transit ridership exports · Output: formal technical memorandum

The City of Terrace requested an independent analysis of BC Transit ridership data against the Service Standard and Performance Guidelines to inform transit planning decisions.

Processed multi-route ridership datasets provided by BC Transit; structured the data in Excel and calculated performance metrics against BCT service standard targets. Identified routes and time periods with statistically significant ridership shortfalls; compiled a formal technical memorandum submitted to the City of Terrace for planning review.